| CPC G11C 7/222 (2013.01) [G11C 11/412 (2013.01)] | 20 Claims |

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1. A semiconductor device comprising:
a memory bank;
a first clock generator including a first transistor configured to receive an external clock signal, the first clock generator being configured to generate a global clock signal that is based on the external clock signal and that controls writing to and reading from the memory bank; and
a second clock generator including a first transistor configured to receive the external clock signal, the second clock generator being configured to generate a pipeline clock signal that is based on the external clock signal and that controls a pipeline operation, which simultaneously and respectively fetches and executes next and current instructions associated with reading from the memory bank, wherein the first transistor of the second clock generator is different from the first transistor of the first clock generator.
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