US 12,272,426 B2
Duty cycle adjuster optimization training algorithm to minimize the jitter associated with DDR5 DRAM transmitter
Arvind Kumar, Palo Alto, CA (US); Dean-Dexter R. Eugenio, Folsom, CA (US); and Santhosh Muskula, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 22, 2021, as Appl. No. 17/354,788.
Prior Publication US 2021/0390991 A1, Dec. 16, 2021
Int. Cl. G11C 7/00 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 8/18 (2006.01); H03K 3/017 (2006.01); H03K 5/156 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 7/1066 (2013.01); G11C 7/1093 (2013.01); G11C 8/18 (2013.01); H03K 3/017 (2013.01); H03K 5/1565 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller comprising:
Input/Output (I/O) interface circuitry, including an input clock signal, configured to be coupled to I/O interface circuitry on a Synchronous Dynamic Random Access Memory (SDRAM) module; and
Duty Cycle Adjuster (DCA) training logic for adjusting a four-phase clock for the SDRAM module including an 0° phase (ICLK), a 90° phase (QCLK), a 180° phase (IBCLK), and a 270° phase (QBCLK), the DCA training logic to:
adjust a duty-cycle ratio for QCLK while holding duty-cycle ratios for IBCLK and QBCLK at predetermined values to determine a first optimized duty-cycle ratio;
adjust the duty-cycle ratio for IBCLK while holding the duty-cycle ratio for QCLK at the first optimized duty-cycle ratio and holding the duty-cycle ratio for QBCLK at a predetermined value to determine a second optimized duty-cycle ratio; and
adjust the duty-cycle ratio for QBCLK while holding the duty-cycle ratio for QCLK at the first optimized duty-cycle ratio and holding the duty-cycle ratio for IBCLK at the second optimized duty-cycle ratio to determine a third optimized duty-cycle ratio.