| CPC G11C 7/20 (2013.01) [G06F 18/214 (2023.01); G06N 20/00 (2019.01); G11C 7/1066 (2013.01); G11C 7/1069 (2013.01); G11C 7/1093 (2013.01); G11C 7/1096 (2013.01); G11C 11/4074 (2013.01); G11C 29/00 (2013.01); G11C 29/023 (2013.01); G11C 29/10 (2013.01); G11C 29/56012 (2013.01); G11C 2029/0407 (2013.01)] | 20 Claims |

|
1. A memory controller comprising:
a training controller configured to
perform training of correcting interface signals exchanged with a memory device,
generate training data that is a result of the training and includes a timing offset for the interface signals, and
output the training data as sample training data when the training data passes a training reference;
a training data storage configured to store training history information including plural pieces of sample training data; and
a machine learning processor configured to update the training reference through machine learning based on the training history information whenever the memory device is booted on,
wherein the machine learning processor is configured to update the training reference by calculating a current training reference by differently reflecting a weight to a previous training reference.
|