US 12,272,424 B2
Reducing spurious write operations in a memory device
Shishir Kumar, Noida (IN); and Vinay Kumar, Aligarh (IN)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Mar. 21, 2023, as Appl. No. 18/124,489.
Claims priority of provisional application 63/322,461, filed on Mar. 22, 2022.
Prior Publication US 2023/0307019 A1, Sep. 28, 2023
Int. Cl. G11C 7/10 (2006.01); G11C 11/40 (2006.01)
CPC G11C 7/1084 (2013.01) [G11C 7/1096 (2013.01); G11C 11/40 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A driver circuitry comprising:
first transistors configured to drive a bitcell of a memory device; and
a first inverter device coupled to the first transistors, and configured to drive the first transistors with a first control signal, wherein the first inverter device comprises:
first inverter circuitry configured to receive a first signal, a first voltage, and a second voltage differing from the first voltage, and generate a first inverted signal based on the first signal, the first voltage and the second voltage; and
second inverter circuitry configured to receive the first inverted signal, the second voltage and a third voltage differing from the second voltage, and generate the first control signal based on the first inverted signal, the third voltage and the second voltage, wherein a voltage value of the third voltage is greater than a voltage value of the second voltage.