US 12,272,421 B2
Creating dynamic latches above a three-dimensional non-volatile memory array
Jiewei Chen, Meridian, ID (US); Mithun Kumar Ramasahayam, Meridian, ID (US); and Tomoko Ogura Iwasaki, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 25, 2022, as Appl. No. 17/895,959.
Prior Publication US 2024/0071430 A1, Feb. 29, 2024
Int. Cl. G11C 7/10 (2006.01)
CPC G11C 7/1039 (2013.01) 17 Claims
OG exemplary drawing
 
1. A method of forming a memory device comprising:
forming a memory array comprising a plurality of memory cells arranged in a plurality of memory strings along a plurality of memory array pillars; and
forming a logic layer disposed above the memory array, the logic layer comprising a plurality of latches arranged along a plurality of logic layer latch pillars, the plurality of latches to store a multi-bit data pattern representing a sequence of bits to be programmed to the plurality of memory cells of the memory array, wherein forming the logic layer disposed above the memory array comprises:
forming a plurality of latch source plates;
forming a plurality of horizontal layers above each of the plurality of latch source plates; and
forming a subset of the plurality of logic layer latch pillars extending vertically from each of the plurality of latch source plates through the plurality of horizontal layers, wherein each intersection of one of the plurality of horizontal layers and one of the plurality of logic layer latch pillars comprises a device forming a portion of one of the plurality of latches in the logic layer.