	US 12,272,420 B2
	Series of parallel sensing operations for multi-level cells
Qing Dong, Hsinchu (TW); Mahmut Sinangil, Campbell, CA (US); Yen-Ting Lin, San Jose, CA (US); Kerem Akarvardar, Hsinchu (TW); Carlos H. Diaz, Los Altos Hills, CA (US); and Yih Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 24, 2023, as Appl. No. 18/357,769.
Application 18/357,769 is a continuation of application No. 17/571,077, filed on Jan. 7, 2022, granted, now 11,735,235.
Application 17/571,077 is a continuation of application No. 16/901,990, filed on Jun. 15, 2020, granted, now 11,238,906, issued on Feb. 1, 2022.
Prior Publication US 2023/0377614 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 13/00 (2006.01); G11C 5/06 (2006.01); G11C 7/08 (2006.01); G11C 7/10 (2006.01); G11C 7/14 (2006.01); G11C 16/26 (2006.01)

CPC G11C 7/08 (2013.01) [G11C 5/06 (2013.01); G11C 7/1012 (2013.01); G11C 16/26 (2013.01); G11C 7/14 (2013.01); G11C 13/004 (2013.01); G11C 2013/0054 (2013.01)]

20 Claims

1. A method, comprising:

selecting a first reference circuit from a first set of reference circuits;

selecting a second reference circuit from a second set of reference circuits;

determining one or more bits of multiple bits of data stored by a multi-level cell, based at least in part on the first reference circuit and the second reference circuit;

selecting a third reference circuit from the first set of reference circuits, according to the determined one or more bits;

selecting a fourth reference circuit from the second set of reference circuits, according to the determined one or more bits; and

determining additional one or more bits of the multiple bits of data stored by the multi-level cell, based at least in part on the third reference circuit and the fourth reference circuit.