US 12,272,418 B2
Performing select gate integrity checks to identify and invalidate defective blocks
Zhongguang Xu, San Jose, CA (US); Zhenlei Shen, Milpitas, CA (US); and Murong Lang, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 6, 2023, as Appl. No. 18/242,884.
Application 18/242,884 is a continuation of application No. 17/550,462, filed on Dec. 14, 2021, granted, now 11,854,644.
Prior Publication US 2023/0420066 A1, Dec. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/34 (2006.01); G06F 3/06 (2006.01); G11C 29/50 (2006.01)
CPC G11C 29/50004 (2013.01) [G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, to perform operations comprising:
receiving, from a host system, an enhanced erase command referencing a block;
performing a lookup to determine whether the block is marked in a grown bad block (GBB) data structure used to track blocks that have a defective select gate, wherein blocks are marked in the GBB data structure in response to determining that a parameter value satisfies a threshold criterion, wherein the parameter value is determined by applying a maximum allowable voltage to a drain select line and measuring a voltage at a select gate; and
responsive to determining that the block is marked in the GBB data structure, discarding the enhanced erase command.