US 12,272,417 B2
Vera detection method to catch erase fail
Parth Amin, Livermore, CA (US); Sai Gautham Thoppa, San Jose, CA (US); and Anubhav Khandelwal, San Jose, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Jul. 21, 2023, as Appl. No. 18/356,786.
Claims priority of provisional application 63/424,648, filed on Nov. 11, 2022.
Prior Publication US 2024/0161858 A1, May 16, 2024
Int. Cl. G11C 29/12 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/16 (2006.01); G11C 16/34 (2006.01); G11C 29/46 (2006.01)
CPC G11C 29/46 (2013.01) [G11C 16/0483 (2013.01); G11C 16/14 (2013.01); G11C 16/16 (2013.01); G11C 16/3445 (2013.01); G11C 29/12005 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a voltage generator configured to ramp up an erase voltage from a steady state voltage towards a target voltage; and
one or more control circuits in communication with the voltage generator, the one or more control circuits configured to connect to non-volatile memory cells arranged as NAND strings, wherein the non-volatile memory cells are arranged in erase blocks, wherein the one or more control circuits are configured to:
detect a failure of a parallel erase of a set of the erase blocks; and
separately test each block in the set in response to the failure of the parallel erase of the set, including for each respective erase block in the set:
provide the erase voltage from the voltage generator to only the respective erase block;
determine that the respective erase block has passed the test responsive to a magnitude of the erase voltage to the respective erase block being above a threshold at a pre-determined time after the voltage generator begins to ramp up the erase voltage; and
determine that the respective erase block has failed the test responsive to the magnitude of the erase voltage to the respective erase block not being above the threshold at the pre-determined time.