US 12,272,416 B2
ATPG testing method for latch based memories, for area reduction
Venkata Narayanan Srinivasan, Greater Noida (IN); Balwinder Singh Soni, Faridabad (IN); and Avneep Kumar Goyal, Greater Noida (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on May 13, 2024, as Appl. No. 18/661,914.
Application 18/661,914 is a continuation of application No. 18/078,714, filed on Dec. 9, 2022, granted, now 12,020,760.
Application 18/078,714 is a continuation of application No. 17/443,556, filed on Jul. 27, 2021, granted, now 11,557,364, issued on Jan. 17, 2023.
Prior Publication US 2024/0296899 A1, Sep. 5, 2024
Int. Cl. G11C 29/00 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 29/14 (2006.01); G11C 29/36 (2006.01); G11C 29/38 (2006.01); G11C 29/12 (2006.01); H03K 19/20 (2006.01)
CPC G11C 29/38 (2013.01) [G11C 7/1084 (2013.01); G11C 7/22 (2013.01); G11C 29/14 (2013.01); G11C 29/36 (2013.01); G11C 2029/1206 (2013.01); G11C 2029/3602 (2013.01); H03K 19/20 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A system configured to be selectively switched between a normal operational mode and a transition testing mode, the system comprising:
a write data register clocked by a clock signal;
a read data register clocked by the clock signal;
a first-in-first-out (FIFO) buffer coupled between the write data register and the read data register, the FIFO buffer including banks of latches configured to store data; and
glue logic including:
a first logic circuit configured to generate an internal write enable signal based on an operational mode of the system;
a second logic circuit configured to generate an internal read valid signal based on the operational mode of the system; and
a third logic circuit configured to generate an internal read enable signal based on the operational mode of the system;
wherein the banks of latches are accessed for reading and writing by a read enable signal and write enable signal based on a read address signal and a write address signal, respectively, in the normal operational mode, and wherein the banks of latches are tested using the internal write enable signal, the internal read enable signal, and the internal read valid signal in the transition testing mode.