US 12,272,415 B2
System and method for testing memory device
Yaochang Chiu, Taoyuan (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Jun. 13, 2023, as Appl. No. 18/209,051.
Prior Publication US 2024/0420788 A1, Dec. 19, 2024
Int. Cl. G11C 29/12 (2006.01); G11C 29/10 (2006.01)
CPC G11C 29/1201 (2013.01) [G11C 29/10 (2013.01); G11C 29/12005 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a memory device configured to operate with a supply voltage having a first value; and
a processor operatively coupled to the memory device and configured to:
generate a write command for writing a first datum to the memory device;
generate a first read command for reading a second datum from the memory device and comparing the first datum and the second datum;
adjust the supply voltage to have a second value different from the first value; and
generate a second read command for reading a third datum from the memory device and comparing the first datum and the third datum for a test result.