US 12,272,409 B2
Flash memory device for adjusting trip voltage using voltage regulator and sensing method thereof
Tae-Hong Kwon, Suwon-si (KR); Kiwhan Song, Suwon-si (KR); and Gyosoo Choo, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 28, 2023, as Appl. No. 18/176,347.
Claims priority of application No. 10-2022-0088787 (KR), filed on Jul. 19, 2022.
Prior Publication US 2024/0029798 A1, Jan. 25, 2024
Int. Cl. G11C 7/22 (2006.01); G11C 16/04 (2006.01); G11C 16/20 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 16/0433 (2013.01); G11C 16/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A flash memory device comprising:
a cell string including a plurality of memory cells;
a page buffer connected to the cell string and a bit line and configured to sense data stored in a selected memory cell from among the plurality of memory cells by precharging a sensing node connected to the bit line; and
a voltage regulator configured to provide a source voltage to the page buffer,
wherein the page buffer comprises
a latch including first and second inverters coupled between a latch node and an inverted latch node, and
a pull-down n-type metal-oxide-semiconductor (“NMOS”) transistor configured to define a trip voltage provided to the latch node based on a result of the sensing of the data stored in the selected memory cell, and
wherein the voltage regulator is configured to adjust the-trip voltage by providing the source voltage to the pull-down NMOS transistor.