US 12,272,408 B2
Partial block read level voltage compensation to decrease read trigger rates
Nagendra Prasad Ganesh Rao, Folsom, CA (US); Paing Z. Htet, Union City, CA (US); Sead Zildzic, Jr., Folsom, CA (US); and Thomas Fiala, Folsom, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 24, 2023, as Appl. No. 18/138,489.
Claims priority of provisional application 63/340,059, filed on May 10, 2022.
Prior Publication US 2023/0368845 A1, Nov. 16, 2023
Int. Cl. G11C 7/00 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 16/08 (2013.01); G11C 16/102 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array comprising a plurality of wordlines coupled with respective memory cells of the memory array; and
control logic operatively coupled with the memory array, the control logic to perform operations comprising:
determining, prior to performing a read operation at one or more strings of the respective memory cells, a number of wordlines that are associated with memory cells that have been programmed, wherein the determining comprises detecting a pass voltage trip point value associated with a pass voltage applied to wordlines of the one or more strings;
adjusting, based on the number of wordlines, a read level voltage for a selected wordline of the one or more strings that is to be read during the read operation; and
causing, during the read operation, the adjusted read level voltage to be applied to the selected wordline.