| CPC G11C 16/24 (2013.01) | 20 Claims |
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1. A memory device, comprising:
a memory cell array comprising memory cells;
a page buffer circuit comprising a plurality of page buffers coupled to the memory cell array, each page buffer comprising a plurality of latches and an internal data line (IDL) arranged to couple to the plurality of latches; and
a cache circuit comprising a plurality of caches,
wherein the IDLs of the plurality of page buffers are configured to be conductively connected together in series to form a data bus (DBUS) that conductively connects the page buffer circuit to the cache circuit for data transfer.
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