| CPC G11C 16/14 (2013.01) [G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); G11C 16/06 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01)] | 15 Claims |
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1. A memory system comprising a non-volatile semiconductor memory device and a memory controller,
the memory device including:
a semiconductor substrate;
a source line provided above the semiconductor substrate
a bit line provided above the semiconductor substrate;
a first select gate line provided above the semiconductor substrate; and
a second select gate line provided above the semiconductor substrate,
a plurality of word lines stacked between the semiconductor substrate and the bit line;
a first semiconductor layer penetrating the first select gate line, the word lines and the second select gate line, and a charge accumulation layer provided between the first semiconductor layer and the first select gate line, between the first semiconductor layer and the word lines and between the first semiconductor layer and the second select gate line, the first semiconductor layer and the charge accumulation layer forming a first select transistor to a gate of which the first select gate line is connected, a plurality of memory cells to gates of which the word lines are connected, respectively and a second select transistor to a gate of which the second select gate line is connected; and
a control circuit configured to perform
an erase operation to bring threshold voltage levels of the memory cells below a first threshold voltage level,
a first write operation to bring the threshold voltage levels of the memory cells above a second threshold voltage level, the first write operation being performed after the erase operation, the second threshold voltage level being higher than the first threshold voltage level, and
a second write operation to bring at least part of the threshold voltage levels of the memory cells above a third threshold voltage level, the second write operation being performed after the first write operation, the third threshold voltage level being higher than the second threshold voltage level,
the memory controller connected to the memory device and configured to send a command to the memory device,
wherein
the control circuit of the memory device is further configured to
upon receipt of a suspend command sent from the memory controller during when the first write operation is being performed, suspend the first write operation,
upon receipt of a first command sent from the memory controller after the first write operation has been suspended, perform a first operation, and
upon receipt of a resume command sent from the memory controller after the first operation has been performed, resume the first write operation.
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