| CPC G11C 16/102 (2013.01) [G11C 16/08 (2013.01); G11C 16/14 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/3404 (2013.01)] | 20 Claims |
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1. A memory device, comprising:
selected word lines coupled to first memory cells;
a first group of unselected word lines coupled to second memory cells;
a second group of unselected word lines coupled to third memory cells; and
a peripheral circuit coupled to the selected word lines, the first group of unselected word lines, and the second group of unselected word lines, wherein the peripheral circuit is configured to:
apply program voltages on the selected word lines;
apply first pass voltages on the first group of unselected word lines;
apply second pass voltages on the second group of unselected word lines, wherein a first maximum value of the first pass voltages is different from a second maximum value of the second pass voltages; and
program memory cells in sequence, the memory cells comprising the first memory cells, the second memory cells, and the third memory cells,
wherein:
the first maximum value of the first pass voltages is a maximum value of all pass voltage pulses of the first group of unselected word lines during program operations of the memory cells coupled to two or more word lines in sequence; and
the second maximum value of the second pass voltages is a maximum value of all pass voltage pulses of the second group of unselected word lines during the program operations of the memory cells coupled to two or more word lines in sequence.
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