US 12,272,400 B2
Semiconductor device and semiconductor system
Shinji Tanaka, Tokyo (JP); Yohei Sawada, Tokyo (JP); and Masao Morimoto, Tokyo (JP)
Assigned to RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed by RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed on Feb. 2, 2023, as Appl. No. 18/163,590.
Claims priority of application No. 2022-016219 (JP), filed on Feb. 4, 2022.
Prior Publication US 2023/0253042 A1, Aug. 10, 2023
Int. Cl. G11C 7/22 (2006.01); G11C 5/14 (2006.01); G11C 7/06 (2006.01); G11C 15/04 (2006.01)
CPC G11C 15/04 (2013.01) [G11C 5/148 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a memory array including a plurality of associative memory cells arranged in a matrix form for storing entries,
wherein the memory array is divided into a plurality of memory blocks that sequentially perform a retrieval operation along a column direction,
the memory array further includes:
a plurality of match lines provided correspondingly to the respective memory blocks and correspondingly to each of memory cell rows;
a plurality of search lines provided correspondingly to the respective memory blocks and correspondingly to each of memory cell columns; and
a plurality of match amplifiers corresponding to the respective memory blocks and respectively provided in the plurality of match lines,
wherein the match lines provided correspondingly to a preceding memory block is set to be shorter than the match line provided correspondingly to a subsequent memory block, and
wherein the memory array further includes a timing control unit for controlling timing of driving the search line of the subsequent memory block based on a length of the match line provided correspondingly to the preceding memory block.