US 12,272,399 B1
Differential programming of two-terminal resistive switching memory with program soaking and adjacent path disablement
Hagop Nazarian, Danville, CA (US)
Assigned to Crossbar, Inc., Santa Clara, CA (US)
Filed by Crossbar, Inc., Santa Clara, CA (US)
Filed on Feb. 26, 2024, as Appl. No. 18/587,443.
Application 18/587,443 is a continuation of application No. 17/710,835, filed on Mar. 31, 2022, granted, now 12,080,347.
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/0069 (2013.01) [G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0038 (2013.01); G11C 13/004 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit, comprising:
an array of non-volatile memory, the array further comprising:
a first electrical line connected to a first terminal of a first non-volatile memory cell of the array;
a second electrical line connected to a first terminal of a second non-volatile memory cell of the array;
a switching circuit connected to a second terminal of the first non-volatile memory cell and connected to a second terminal of the second non-volatile memory cell;
a third electrical line connected to the switching circuit for selectively connecting or disconnecting the second terminals to a low voltage, or ground;
a programming power source configured to supply an electrical power signal for the array of non-volatile memory; and
a controller configured to execute a program operation on the first non-volatile memory cell and on the second non-volatile memory cell, wherein the program operation comprises:
connect the first and second electrical lines to the programming power source;
supply the electrical power signal at the programming power source for a program cycle duration;
activate the third electrical line and connect the second terminals to the low voltage, or ground; and
maintain the electrical power signal at the programming power source for the program cycle duration, wherein in response to a program event that increases electrical conductivity of the first non-volatile memory cell, a program voltage across the second non-volatile memory cell in response to the programming signal is reduced in magnitude.