US 12,272,315 B2
Method of driving scan circuit, scan circuit, and display apparatus
Shuai Hou, Beijing (CN); Shuai Chen, Beijing (CN); and Bin Wang, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 18/041,993
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed May 10, 2022, PCT No. PCT/CN2022/091837
§ 371(c)(1), (2) Date Feb. 16, 2023,
PCT Pub. No. WO2023/216086, PCT Pub. Date Nov. 16, 2023.
Prior Publication US 2024/0265876 A1, Aug. 8, 2024
Int. Cl. G09G 3/36 (2006.01); G09G 3/3233 (2016.01); G09G 3/3266 (2016.01)
CPC G09G 3/3266 (2013.01) [G09G 3/3233 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0286 (2013.01); G09G 2320/0233 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method of driving a scan circuit, comprising providing N1 number of first clock signals time-sequentially to (k*N1) number of stages of the scan circuit, respectively, the (k*N1) number of stages comprising M number of groups, a respective group of the M number of groups comprising one or more stages of the scan circuit, N1, k, M being integers; N1≥2, k≥1; M≥2;
wherein a respective first clock signal of the N1 number of first clock signals comprises a first level component and a second level component following the first level component;
a m-th group of the M number of groups is configured to receive first clock signals before a (m+1)-th group of the M number of groups receives first clock signals, 1≤m≤(M−1);
with respect to N2 number of data enabling signals, a difference between a starting point of a first level component of an n1-th first clock signal and a starting point of an n2-th data enabling signal of the N2 number of data enabling signals is equal to tm1, N2=N1, n2=n1;
values of tm1 for first clock signals provided to different groups of the M number of groups are different; and
the N2 number of data enabling signals are signals provided to a timing controller coupled to the scan circuit, and configured to control a timing of data output;
wherein, with respect to N3 number of first reference periods, a difference between a starting point of a first level component of an n1-th first clock signal and a starting point of an n3-th first reference period of the N3 number of first reference periods is equal to tmA, N3=N1, n3=n1;
durations of the N3 number of first reference periods are the same;
an N3-th first reference period of the N3 number of first reference periods overlaps with an N1-th period of the N1 number of first clock signals;
at least a first period of the N1 number of first clock signals is partially non-overlapping with a 1st first reference period of the N3 number of first reference periods; and
values of tmA for first clock signals provided to different groups of the M number of groups are different.