US 12,272,314 B2
Display substrate, preparation method thereof, and display apparatus
Long Han, Beijing (CN); Guangliang Shang, Beijing (CN); and Libin Liu, Beijing (CN)
Assigned to BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/771,016
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed May 27, 2021, PCT No. PCT/CN2021/096497
§ 371(c)(1), (2) Date Dec. 1, 2022,
PCT Pub. No. WO2022/246756, PCT Pub. Date Dec. 1, 2022.
Prior Publication US 2024/0144885 A1, May 2, 2024
Int. Cl. G09G 3/3266 (2016.01); G11C 19/28 (2006.01)
CPC G09G 3/3266 (2013.01) [G11C 19/28 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A display substrate, comprising a display region and a non-display region, wherein:
the non-display region is provided with a gate drive circuit, the gate drive circuit comprises a plurality of cascaded shift register units, and a shift register unit is connected with at least one power supply line;
the shift register unit comprises a first output circuit and a second output circuit; the first output circuit is connected with a first group of clock signal lines, and the second output circuit is connected with the first group of clock signal lines and a second group of clock signal lines;
in a first direction, the first group of clock signal lines and the at least one power supply line are located between the first output circuit and the second output circuit, and the second group of clock signal lines are located on a side of the second output circuit away from the first group of clock signal lines;
the first output circuit comprises a first node control sub-circuit, a second node control sub-circuit, and a first output sub-circuit;
the first node control sub-circuit is connected with an input terminal, a first output terminal, a first clock terminal, a second clock terminal, a third clock terminal, a first power supply terminal, a second power supply terminal, a first node, and a second node, and is configured to control potentials of the first node and the second node under control of the first clock terminal, the third clock terminal, and the input terminal;
the second node control sub-circuit is connected with the first node, the second node, the second power supply terminal, and the first output terminal, and is configured to maintain the potentials of the first node and the second node;
the first output sub-circuit is connected with the first node, the second node, the second clock terminal, the second power supply terminal, and the first output terminal, and is configured to control the first output terminal to output a first output signal under control of the first node and the second node; and
the second node control sub-circuit, the first output sub-circuit, and the first node control sub-circuit are sequentially arranged along the first direction.