| CPC G09G 3/3233 (2013.01) [G09G 3/3266 (2013.01); G09G 3/3291 (2013.01); G09G 2310/0208 (2013.01); G09G 2320/0233 (2013.01)] | 10 Claims |
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1. A pixel circuit of a display apparatus, comprising:
a driving transistor configured to include a gate electrode coupled with a gate node, a drain electrode coupled with a high level pixel power source, and a source electrode coupled with a source node;
a light emitting device configured to include an anode electrode coupled with the source node and a cathode electrode coupled with a low level pixel power source;
a first transistor turned on based on a first scan signal having an on level to apply an initialization voltage to the gate node;
a second transistor turned on based on a second scan signal having an on level to apply a reference voltage to the source node;
a first capacitor coupled between the gate node and the source node;
a second capacitor coupled with the source node at one electrode thereof;
a third transistor turned on based on a third scan signal having an on level to couple the gate node with the other electrode of the second capacitor; and
a fourth transistor turned on based on a fourth scan signal having an on level to apply a data voltage to the gate node,
wherein one frame comprises an initialization period, a sensing period, a writing period, and an emission period which are arranged in a time order,
wherein the first scan signal is input at the on level in the initialization period and the sensing period,
the second scan signal is input at the on level in only the initialization period,
the third scan signal is input at an off level in only the sensing period, and
the fourth scan signal is input at the on level in only the writing period.
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