US 12,272,303 B2
Driving circuitry, driving method, driving module, and display device
Ziyang Yu, Beijing (CN); Haijun Qiu, Beijing (CN); Ming Hu, Beijing (CN); Zhiliang Jiang, Beijing (CN); Tianyi Cheng, Beijing (CN); Jianpeng Wu, Beijing (CN); Mengqi Wang, Beijing (CN); Qi Wei, Beijing (CN); Wenbo Chen, Beijing (CN); Tiaomei Zhang, Beijing (CN); Sifei Ai, Beijing (CN); Cong Liu, Beijing (CN); and Qian Xu, Beijing (CN)
Assigned to CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 18/294,003
Filed by CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed May 23, 2023, PCT No. PCT/CN2023/095760
§ 371(c)(1), (2) Date Jan. 31, 2024,
PCT Pub. No. WO2024/239228, PCT Pub. Date Nov. 28, 2024.
Prior Publication US 2025/0078740 A1, Mar. 6, 2025
Int. Cl. G09G 3/3225 (2016.01)
CPC G09G 3/3225 (2013.01) [G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2320/0247 (2013.01); G09G 2330/021 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A driving circuitry, comprising a driving signal generation circuitry, a gating circuitry, an output control circuitry, and an output circuitry, wherein
the driving signal generation circuitry is electrically coupled to an (N−1)th-level driving signal output end and an Nth-level driving signal output end, and configured to perform a shifting operation on an (N−1)th-level driving signal from the (N−1)th-level driving signal output end to obtain and output an Nth-level driving signal through the Nth-level driving signal output end;
the gating circuitry is electrically coupled to a first node, a gating input end, and a gating control end, and configured to write a gating input signal from the gating input end into the first node under the control of a gating control signal from the gating control end;
a first end of the output control circuitry is electrically coupled to the Nth-level driving signal output end, and a second end of the output control circuitry is electrically coupled to the first node, and the output control circuitry is configured to perform an NAND operation on the Nth-level driving signal and a potential at the second end of the output control circuitry to obtain a first output signal; and
the output circuitry is configured to perform phase inversion on the first output signal to obtain and provide an output driving signal through an output driving end,
where N is a positive integer.