US 12,272,299 B1
Compact memory-in-pixel display structure
Juhan Kim, Santa Clara, CA (US); Sanjay Raj Parihar, Austin, TX (US); Mahbub Rashed, Cupertino, CA (US); and Zahir Yilmaz Alpaslan, San Marcos, CA (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Oct. 6, 2023, as Appl. No. 18/482,114.
Int. Cl. G09G 3/32 (2016.01); G11C 11/419 (2006.01); H10B 10/00 (2023.01)
CPC G09G 3/32 (2013.01) [G11C 11/419 (2013.01); H10B 10/12 (2023.02); H10B 10/18 (2023.02); G09G 2300/0439 (2013.01); G09G 2300/0814 (2013.01); G09G 2300/0857 (2013.01); G09G 2310/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
an array of memory cells on an insulator layer over a Pwell in a semiconductor substrate;
a driving circuit on the insulator layer over an Nwell in the semiconductor substrate, wherein the Nwell is positioned laterally adjacent to the Pwell and wherein the driving circuit is connected to an anode of a light emitting diode; and
a logic circuit on the insulator layer connected to the array of the memory cells and the driving circuit, wherein the logic circuit includes P-type transistors on the insulator layer over the Nwell and N-type transistors on the insulator layer over the Pwell.