US 12,272,297 B2
Scan driver
Yang Hwa Choi, Yongin-si (KR); and Bo Yong Chung, Yongin-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-Si (KR)
Filed by Samsung Display Co., Ltd., Yongin-Si (KR)
Filed on Oct. 2, 2023, as Appl. No. 18/375,566.
Application 18/375,566 is a continuation of application No. 17/827,272, filed on May 27, 2022, granted, now 11,817,042.
Application 17/827,272 is a continuation of application No. 16/941,140, filed on Jul. 28, 2020, granted, now 11,348,513, issued on May 31, 2022.
Claims priority of application No. 10-2019-0105870 (KR), filed on Aug. 28, 2019.
Prior Publication US 2024/0029642 A1, Jan. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/32 (2016.01); G09G 3/3266 (2016.01)
CPC G09G 3/32 (2013.01) [G09G 3/3266 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0264 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/06 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A scan driver comprising:
scan stages,
wherein a first scan stage among the scan stages is configured to transfer a first previous carry signal of a first previous carry line to a Q node and output a carry signal, a sensing signal, and a scan signal respectively in response to a voltage of the Q node,
wherein the first scan stage is further configured to store a second previous carry signal of a second previous carry line in a first capacitor, transmit a signal of a first voltage level to a first node in response to a voltage stored in the first capacitor, and connect the first node to the Q node in response to a third control signal of a third control line,
wherein the first scan stage discharges the first capacitor to a second voltage level in response to a fourth control signal of a fourth control line regardless of the first previous carry signal,
wherein the first voltage level is higher than the second voltage level,
wherein the first scan stage includes:
a second transistor including a first electrode electrically connected to the first previous carry line, a second electrode electrically connected to the Q node, and a gate electrode electrically connected to the first electrode of the second transistor;
a ninth transistor including a first electrode electrically connected to a carry clock line, a second electrode electrically connected to a carry line, and a gate electrode electrically connected to the Q node;
a first transistor including a first electrode electrically connected to a scan clock line, a second electrode electrically connected to a scan line, and a gate electrode electrically connected to the Q node;
a sixth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the Q node, and a gate electrode electrically connected to the third control line;
a fifth transistor including a first electrode electrically connected to a second control line, a second electrode electrically connected to the first node, and a gate electrode;
a nineteenth transistor electrically connected to the gate electrode of the fifth transistor and including a gate electrode electrically connected to the fourth control line;
a thirteenth transistor including a first electrode electrically connected to the carry line, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a QB node;
a seventeenth transistor including a first electrode electrically connected to the scan line, a second electrode electrically connected to a second power line, and a gate electrode electrically connected to the QB node; and
a seventh transistor including a gate electrode electrically connected to the Q node, a first electrode electrically connected to the second control line, and a second electrode electrically connected to the first node, and
wherein the first capacitor electrically connected between the second control line and the gate electrode of the fifth transistor.