| CPC G09G 3/32 (2013.01) [H01L 25/167 (2013.01); H01L 27/124 (2013.01); G09G 2300/026 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0259 (2013.01); H01L 24/05 (2013.01); H01L 24/16 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05171 (2013.01); H01L 2224/05179 (2013.01); H01L 2224/0518 (2013.01); H01L 2224/05561 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/05686 (2013.01); H01L 2224/16145 (2013.01); H01L 2924/013 (2013.01); H01L 2924/0549 (2013.01); H01L 2924/12041 (2013.01)] | 17 Claims |

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1. A display device comprising:
a scan write line configured to receive a scan write signal;
a scan initialization line configured to receive a scan initialization signal;
a sweep signal line configured to receive a sweep signal;
a first data line configured to receive a first data voltage;
a second data line configured to receive a second data voltage; and
a subpixel connected to the scan write line, the scan initialization line, the sweep signal line, the first data line, and the second data line, wherein:
the subpixel comprises a light-emitting element, a first pixel driver comprising a first transistor configured to generate a control current according to the first data voltage of the first data line, a second pixel driver comprising an eighth transistor configured to generate a driving current applied to the light-emitting element according to the second data voltage of the second data line, and a third pixel driver configured to control a period in which the driving current is applied to the light-emitting element according to the control current of the first pixel driver;
the third pixel driver comprises a fifteenth transistor electrically connected to one electrode of the eighth transistor; and
the display device further comprises a bridge electrode connecting the one electrode of the eighth transistor and one electrode of the fifteenth transistor that are spaced from each other, the bridge electrode being at a different layer from at least one of the eighth transistor or the fifteenth transistor, wherein:
the one electrode of the eighth transistor is connected to the bridge electrode through a first bridge connection electrode;
the one electrode of the fifteenth transistor is connected to the bridge electrode through a fourth bridge connection electrode, and
the first bridge connection electrode is located between the sweep signal line and the scan write line.
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