US 12,272,290 B2
Flat panel detector for photoelectric detection and method performed by the flat panel detector
Feng Liu, Beijing (CN); Chuncheng Che, Beijing (CN); and Shuai Xu, Beijing (CN)
Assigned to BEIJING BOE SENSOR TECHNOLOGY CO., LTD., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 18/015,631
Filed by Beijing BOE Sensor Technology Co., Ltd., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Dec. 29, 2021, PCT No. PCT/CN2021/142361
§ 371(c)(1), (2) Date Jan. 11, 2023,
PCT Pub. No. WO2023/123017, PCT Pub. Date Jul. 6, 2023.
Prior Publication US 2024/0242657 A1, Jul. 18, 2024
Int. Cl. G09G 3/20 (2006.01)
CPC G09G 3/2092 (2013.01) [G09G 2300/0404 (2013.01); G09G 2310/08 (2013.01); G09G 2360/14 (2013.01); G09G 2380/08 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A flat panel detector, comprising:
a plurality of pixel units arranged in an array, wherein each of the plurality of pixel units comprises a plurality of pixels arranged in a K×K sub-array, each of the plurality of pixels is configured to provide a photoelectric signal, and K is an odd number greater than 1;
a gate driving circuit connected to a plurality of rows of pixel units in the array, wherein the gate driving circuit is configured to, in an ith detecting period, turn on an ith row of pixel units under control of a gate control signal, so as to cause K rows of pixels in each turned-on pixel unit to generate photoelectric signals, wherein i is an integer greater than or equal to 1;
a readout circuit connected to a plurality of columns of pixel units in the array, wherein the readout circuit is configured to, in the ith detecting period, read photoelectric signals from K columns of pixels in each column of pixel units under control of a readout control signal, and generate image data for each pixel unit according to the photoelectric signals read from the each pixel unit; and
a control circuit connected to the gate driving circuit and the readout circuit, wherein the control circuit is configured to provide the gate control signal to the gate driving circuit, provide the readout control signal to the readout circuit, and perform data processing based on the image data provided by the readout circuit,
wherein the gate control signal comprises a clock signal and an enable signal,
wherein the gate driving circuit comprises a plurality of shift register units cascaded into stages, wherein a cascade output terminal of an nth stage of shift register unit is connected to an input terminal of a (n+1)th stage of shift register unit, a signal output terminal of each shift register unit is connected to one row of pixels, a clock terminal of each shift register unit is connected to receive a clock signal, an enable terminal of each shift register unit is connected to receive an enable signal, and each shift register unit is configured to provide a cascade output signal at the cascade output terminal and provide a gate driving signal at the signal output terminal, based on a signal at the input terminal and the enable signal at the enable terminal under control of the clock signal at the clock terminal, and
wherein the shift register unit comprises a D flip-flop, an AND gate, a level shifter and an output buffer circuit, a first input terminal of the D flip-flop acts as the clock terminal of the shift register unit, a second input terminal of the D flip-flop acts as the input terminal of the shift register unit, an output terminal of the D flip-flop acts as the cascade output terminal of the shift register unit, a first input terminal of the AND gate acts as the enable terminal of the shift register unit, a second input terminal of the AND gate is connected to an output terminal of the D flip-flop, an output terminal of the AND gate is connected to an input terminal of the level shifter, an output terminal of the level shifter is connected to an input terminal of the output buffer circuit, and an output terminal of the output buffer circuit acts as the signal output terminal of the shift register unit.