| CPC G06N 3/063 (2013.01) [G06N 3/04 (2013.01); G06N 3/082 (2013.01)] | 12 Claims |

|
1. A neural network apparatus, the apparatus comprising:
a plurality of node buffers configured to store first split data being least significant bit (LSB) N/2 bits of an input node data and second split data being most significant bit (MSB) N/2 bits of the input node data, the input node data being N bits (N is a natural number greater than or equal to 2); and
one or more processors configured to:
output the first split data to an operation circuit for a neural network operation on an index-by-index basis,
shift the second split data by N/2 bits,
output the second split data to the operation circuit on the index-by-index basis,
based on whether either one or both of the first and second split data includes all zero values, selectively determine whether to skip a neural network operation for the either one or both of the first and second split data or otherwise perform the neural network operation, and
in response to determining to skip the neural network operation, replace an entirety of the either one or both of the first and second split data with partial data of next input node data having a same index.
|