CPC G06F 8/41 (2013.01) [G06F 13/4022 (2013.01); G06N 10/20 (2022.01); G06N 10/40 (2022.01); G06N 10/70 (2022.01); H04B 10/70 (2013.01); H04Q 11/0005 (2013.01); H04Q 2011/0043 (2013.01)] | 23 Claims |
1. A circuit comprising:
a resource state interconnect having a plurality of output paths to output a resource state during each of a plurality of operating cycles, wherein each resource state is a quantum system of multiple entangled physical qubits, wherein the physical qubits are photonic qubits, and wherein different physical qubits of the resource state are output on a different ones of the output paths;
a plurality of reconfigurable fusion circuits, each of the plurality of reconfigurable fusion circuits being configured to receive two input physical qubits and to selectably perform either a projective entangling measurement between the two input physical qubits or one of a plurality of single-qubit measurements on each of the two input physical qubits, thereby producing measurement outcome data;
a plurality of routing switches, each routing switch having an input path coupled to a respective one of the output paths of the resource state interconnect and a plurality of output routing paths selectably coupled to the input path, wherein, for each routing switch, the plurality of output routing paths includes:
a first local path, wherein the first local paths of different ones of the routing switches introduce different delays;
a plurality of internal port routing paths; and
a plurality of port transfer paths that exit the circuit; and
a plurality of external port routing paths to receive physical qubits from a plurality of external circuits,
wherein the plurality of reconfigurable fusion circuits includes:
a plurality of local fusion circuits, wherein each local fusion circuit is coupled to respective first local routing paths of two of the routing switches; and
a plurality of port fusion circuits, wherein each port fusion circuit has a first input coupled to one of the internal port routing paths of one of the routing switches and a second input coupled to one of the of the external port routing paths.
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