US 12,271,678 B2
Integrated circuit with constrained metal line arrangement, method of using, and system for using
XinYong Wang, Hsinchu (TW); Qiquan Wang, Hsinchu (TW); Li-Chun Tien, Hsinchu (TW); and Yuan Ma, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and TSMC CHINA COMPANY, LIMITED, Shanghai (CN)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and TSMC CHINA COMPANY, LIMITED, Shanghai (CN)
Filed on Jul. 24, 2023, as Appl. No. 18/357,731.
Application 18/357,731 is a continuation of application No. 17/342,006, filed on Jun. 8, 2021, granted, now 11,748,550.
Application 17/342,006 is a continuation of application No. 16/670,000, filed on Oct. 31, 2019, granted, now 11,030,382, issued on Jun. 8, 2021.
Claims priority of application No. 201910974639.2 (CN), filed on Oct. 14, 2019.
Prior Publication US 2023/0367949 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/398 (2020.01); G06F 30/394 (2020.01); H05K 1/02 (2006.01)
CPC G06F 30/398 (2020.01) [G06F 30/394 (2020.01); H05K 1/0268 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of making an integrated circuit, comprising:
dividing, in a first layer of an integrated circuit layout, a first arrangement of metal lines into a first set of metal lines and a second set of metal lines, wherein the first set of metal lines is between the second set of metal lines and a periphery of the integrated circuit layout, wherein the first arrangement of metal lines is configured to electrically connect to a plurality of contacts connected to a second layer of the integrated circuit layout after a manufacturing process; and
adjusting a metal line perimeter of at least one metal line in the second set of metal lines to make a second arrangement of metal lines, wherein each adjusted metal line perimeter is separated from contacts in the second layer of the integrated circuit layout by at least a check distance.