US 12,271,676 B2
Parallel mask rule checking on evolving mask shapes in optical proximity correction flows
Kumara Narasimha Sastry Kunigal, Portland, OR (US); Saumyadip Mukhopadhyay, Beaverton, OR (US); Kasyap Thottasserymana Vasudevan, Folsom, CA (US); and Vivek Kumar Singh, Portland, OR (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Mar. 11, 2022, as Appl. No. 17/693,161.
Prior Publication US 2023/0289509 A1, Sep. 14, 2023
Int. Cl. G06F 30/398 (2020.01); G03F 1/36 (2012.01); G03F 7/00 (2006.01); G06F 119/18 (2020.01)
CPC G06F 30/398 (2020.01) [G03F 1/36 (2013.01); G03F 7/70441 (2013.01); G06F 2119/18 (2020.01)] 21 Claims
OG exemplary drawing
 
1. A computer-implemented method, comprising:
receiving a set of edges that define mask shapes for fabrication of an integrated circuit;
partitioning the mask shapes of the integrated circuit into portions;
correcting optical proximity correction (OPC) errors caused by optical lithography effects for each portion containing at least one OPC error;
identifying at least one mask manufacturing rule violation corresponding to the mask shapes for a portion of the portions, wherein the at least one mask manufacturing rule violation results from at least one mask shape change to compensate for the at least one OPC error;
computing, in parallel, adjustments for the set of edges to reduce or remove the at least one mask manufacturing rule violation; and
adjusting at least one edge in the set of edges according to the computed adjustments to produce an adjusted set of edges.