US 12,271,672 B1
Deterministic parallel routing approach for accelerating pathfinder-based algorithms
Umair Farooq Siddiqi, Dhahran (SA)
Assigned to KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS, Dhahran (SA)
Filed by KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS, Dhahran (SA)
Filed on Aug. 14, 2024, as Appl. No. 18/804,644.
Int. Cl. G06F 30/30 (2020.01); G06F 30/347 (2020.01); G06F 30/394 (2020.01); G06F 30/396 (2020.01)
CPC G06F 30/347 (2020.01) [G06F 30/394 (2020.01); G06F 30/396 (2020.01)] 16 Claims
OG exemplary drawing
 
1. A field programmable gate array (FPGA) routing tool in a computer-aided design system, comprising:
an input device for receiving a netlist having nets with source nodes, sink nodes, and a plurality of intermediate nodes at fixed positions; and
processing circuitry configured with
a design router for building non-overlapping routing trees for all nets, including finding a routing tree for each net that connects the source nodes to the sink nodes without exceeding a capacity of fixed routing resources available on the FPGA;
the design router with incremental routing that:
applies deterministic parallel routing to a window of initial iterations having a high routing workload, where the window of initial iterations covers a range from a first iteration to an i-th iteration, and
applies sequential routing to all iterations after the i-th iteration; and
a display device to continuously display interconnections and a routing utilization while the routing trees are being determined.