US 12,271,670 B2
Testbench for sub-design verification
Rajvinder S. Klair, San Jose, CA (US); Dhiraj Kumar Prasad, Hyderabad (IN); Saikat Bandyopadhyay, San Jose, CA (US); Ashish Kumar Jain, Hyderabad (IN); Shiyao Ge, San Jose, CA (US); Tapodyuti Mandal, Hyderabad (IN); and Miti Joshi, Hyderabad (IN)
Assigned to Xilinx, Inc., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on Feb. 4, 2022, as Appl. No. 17/650,035.
Prior Publication US 2023/0252212 A1, Aug. 10, 2023
Int. Cl. G06F 30/333 (2020.01); G06F 30/327 (2020.01); G06F 30/3308 (2020.01)
CPC G06F 30/333 (2020.01) [G06F 30/327 (2020.01); G06F 30/3308 (2020.01)] 17 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving, using computer hardware, a selection of a selected sub-design of a circuit design, wherein the selected sub-design is one of a plurality of sub-designs of the circuit design;
generating, using the computer hardware, a list of port-level signals for the selected sub-design;
extracting, using the computer hardware, one or more parameter values corresponding to the selected sub-design from the circuit design;
using the computer hardware, logging switching activity only for each port-level signal from the list in a switching activity file while running a circuit design testbench for the circuit design with the selected sub-design in scope; and
using the computer hardware, generating, from the list, the switching activity file, and the one or more parameter values, a sub-design testbench for the selected sub-design by, at least in part:
generating a hardware description language testbench template that includes the port-level signals and the one or more parameter values;
generating a vector source file based on the switching activity of the port-level signals from the switching activity file; and
including the vector source file within the hardware description language testbench template resulting in the sub-design testbench.