US 12,271,669 B1
Executing instruction sequences generated from software interactions as part of formal verification of a design under test
Uri Leder, Lotem (IL); Ori Ariel, Ma'ale Adumim (IL); Assaf Fainer, Kefar Sava (IL); Simaan Bahouth, Shefar'am (IL); Max Chvalevsky, Mevaseret Zion (IL); and Itai Kahana, Lod (IL)
Assigned to Amazon Technologies, Inc., Seattle, WA (US)
Filed by Amazon Technologies, Inc., Seattle, WA (US)
Filed on Mar. 30, 2022, as Appl. No. 17/709,192.
Int. Cl. G06F 30/30 (2020.01); G06F 30/3323 (2020.01); G06F 30/367 (2020.01)
CPC G06F 30/3323 (2020.01) [G06F 30/367 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a processor; and
a memory, storing program instructions that when executed by the processor, cause the processor to implement a verification system, the verification system configured to:
receive, via an interface of the verification system, an integrated circuit design under test;
obtain a plurality of software-instructed commands to be performed to the design under test formatted according to an interface implemented by the design under test;
generate a testbench for the design under test in a hardware description and verification language that includes a sequence to perform the plurality of software-instructed commands to the design under test before performing formal verification on the design under test;
execute the testbench with respect to the design under test to perform the sequence to the design under test and to perform formal verification on the design under test; and
provide, via the interface, a result of the execution of the testbench.