US 12,271,668 B1
Finding equivalent classes of hard defects in stacked MOSFET arrays
Mayukh Bhattacharya, Palo Alto, CA (US); Michal Jerzy Rewienski, Gdansk (PL); Shan Yuan, San Jose, CA (US); Michael Durr, Livermore, CA (US); and Chih Ping Antony Fan, Saratoga, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Sep. 19, 2023, as Appl. No. 18/370,339.
Application 18/370,339 is a continuation of application No. 17/400,360, filed on Aug. 12, 2021, granted, now 11,797,737.
Application 17/400,360 is a continuation in part of application No. 17/221,175, filed on Apr. 2, 2021, abandoned.
Claims priority of provisional application 63/004,276, filed on Apr. 2, 2020.
Int. Cl. G06F 30/33 (2020.01); G06F 30/327 (2020.01)
CPC G06F 30/33 (2020.01) [G06F 30/327 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
identifying, in a circuit netlist, a transistor array comprising a plurality of transistor sharing gate and bulk terminals;
determining electrical defects for the plurality of transistors in the transistor array;
grouping the electrical defects into a hierarchy of defect classes based on a topological equivalence and an electrical equivalence of the electrical defects in the transistor array; and
performing, by a processor, a defect simulation on an electrical defect in the hierarchy of defect classes.