US 12,271,667 B2
System on chip (SOC) current profile model for integrated voltage regulator (IVR) co-design
Haohua Zhou, Fremont, CA (US); Tze-Chiang Huang, Saratoga, CA (US); and Mei Hsu Wong, Saratoga, CA (US)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 5, 2023, as Appl. No. 18/329,109.
Application 18/329,109 is a continuation of application No. 17/222,108, filed on Apr. 5, 2021, granted, now 11,669,664.
Application 17/222,108 is a continuation of application No. 16/599,823, filed on Oct. 11, 2019, granted, now 10,970,439, issued on Apr. 6, 2021.
Claims priority of provisional application 62/857,373, filed on Jun. 5, 2019.
Claims priority of provisional application 62/772,966, filed on Nov. 29, 2018.
Prior Publication US 2024/0012969 A1, Jan. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/30 (2020.01); G06F 30/367 (2020.01); G06F 30/39 (2020.01); H01L 23/50 (2006.01); H01L 23/528 (2006.01); H01L 23/538 (2006.01)
CPC G06F 30/30 (2020.01) [G06F 30/367 (2020.01); G06F 30/39 (2020.01); H01L 23/50 (2013.01); H01L 23/5286 (2013.01); H01L 23/5384 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
conducting a first co-simulation of a first design stage for a System on Chip (SOC) and an Integrated Voltage Regulator (IVR);
determining whether the SOC and the IVR pass the first co-simulation;
if the SOC and the IVR do not pass the first co-simulation, then refining specification data of the SOC and/or refining first design data of the IVR and repeating the first co-simulation;
if the SOC and the IVR pass the first co-simulation, then conducting a second co-simulation of a second design stage for the SOC and the IVR;
determining whether the SOC and the IVR pass the second co-simulation;
if the SOC and the IVR do not pass the second co-simulation, then refining the specification data of the SOC and/or refining the design data of the IVR and repeating the second co-simulation;
if the SOC and the IVR pass the second co-simulation, then conducting a third co-simulation of a third design stage for the SOC and the IVR;
determining whether the SOC and the IVR pass the third co-simulation;
if the SOC and the IVR do not pass the third co-simulation, then refining the specification data of the SOC and/or refining the design data of the IVR and repeating the third co-simulation;
if the SOC and the IVR pass the third co-simulation, then finalizing designs for the SOC and the IVR.