US 12,271,653 B2
Audio processing apparatus and audio processing method for dynamically adjusting audio clock
Zhen-Peng Yang, Jiangsu Province (CN); Dong-Yu He, Jiangsu Province (CN); and Jian Sun, Jiangsu Province (CN)
Assigned to REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed on Dec. 12, 2022, as Appl. No. 18/079,112.
Claims priority of application No. 202210095189.1 (CN), filed on Jan. 26, 2022.
Prior Publication US 2023/0236790 A1, Jul. 27, 2023
Int. Cl. G06F 3/16 (2006.01); H03L 7/08 (2006.01)
CPC G06F 3/162 (2013.01) [H03L 7/08 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An audio processing apparatus for dynamically adjusting an audio clock, the audio processing apparatus comprising:
a first interface configured to receive audio data from a host;
a buffer coupled to the first interface, wherein the buffer is configured to store the audio data in a first sampling stage to generate a first audio packet, and determine relationships between a data volume of the first audio packet and a first upper threshold and a first lower threshold;
a clock generator configured to generate a clock signal;
a processor configured to control the clock generator to adjust a frequency of the clock signal;
a second interface coupled to the buffer, wherein the second interface is configured to output the first audio packet from the buffer and the clock signal from the clock generator to a codec apparatus, such that the codec apparatus reads and processes the first audio packet according to the clock signal,
wherein, in response to the buffer determining that the data volume of the first audio packet is less than the first lower threshold, the buffer is configured to output an underflow interrupt signal to the processor, and the processor is configured to control the clock generator according to the underflow interrupt signal, so as to reduce the frequency of the clock signal,
wherein, in response to the buffer determining that the data volume of the first audio packet is greater than the first upper threshold, the buffer is configured to output an overflow interrupt signal to the processor, and the processor is configured to control the clock generator according to the overflow interrupt signal, so as to increase the frequency of the clock signal.