US 12,271,632 B2
Method and non-transitory computer-readable storage medium and apparatus for executing host write commands
Shen-Ting Chiu, Miaoli County (TW)
Assigned to SILICON MOTION, INC., Zhubei (TW)
Filed by Silicon Motion, Inc., Zhubei (TW)
Filed on Oct. 24, 2023, as Appl. No. 18/383,239.
Claims priority of application No. 202211598950.X (CN), filed on Dec. 14, 2022.
Prior Publication US 2024/0201902 A1, Jun. 20, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0625 (2013.01); G06F 3/0679 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method for executing host write commands, performed by a processing unit of a flash controller, comprising:
providing a sequential-write command queue (SCQ), a random-write command queue (RCQ) and a mark queue, wherein the SCQ stores a plurality of sequential write commands, the RCQ stores a plurality of random write commands, the mark queue comprises a record indicating that a conflicting sequential write command and/or a conflicting random write command needs to be processed in advance;
when a specific condition is met, obtaining a first logical address range carried in the conflicting sequential write command and second logical address ranges carried in the sequential write commands earlier than the conflicting sequential write command from the SCQ, and/or a third logical address range carried in the conflicting random write command and fourth logical address ranges carried in the random write commands earlier than the conflicting random write command from the RCQ according to content of the record;
reading user data of the first logical address range from a first address of a random access memory (RAM) and user data of the second logical address ranges from second addresses of the RAM, and/or user data of the third logical address range from a third address of the RAM and user data of the fourth logical address ranges from fourth addresses of the RAM; and
programming the user data of the first logical address range and the second logical address ranges, and/or the user data of the third logical address range and the fourth logical address ranges into a flash module,
wherein the specific condition is met during a time period between receptions of a first instruction and a second instruction from a host side, where the first instruction instructs the flash controller to enter a sleep mode or a power saving mode, and the second instruction instructs the flash controller to leave the sleep mode or the power saving mode.