US 12,271,627 B2
Off-chip memory shared by multiple processing nodes
Michael John Austin, Austin, TX (US); and Dmitri Tikhostoup, Markham (CA)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed on Sep. 30, 2022, as Appl. No. 17/937,292.
Prior Publication US 2024/0111452 A1, Apr. 4, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first integrated circuit configured to access a first memory via a first communication channel, wherein a communication channel supports data transmission comprising at least requests and responses between a single source and a single destination; and
a second integrated circuit configured to access the first memory via a second communication channel, based at least in part on an indication received via a third communication channel that the first integrated circuit accessed the first memory.