US 12,271,624 B2
Methods and systems for processing read-modify-write requests
Gary S. Goldman, Los Altos, CA (US); and Ashwin Radhakrishnan, Fremont, CA (US)
Assigned to Recogni Inc., San Jose, CA (US)
Filed by Recogni Inc., San Jose, CA (US)
Filed on Mar. 13, 2023, as Appl. No. 18/183,034.
Application 18/183,034 is a continuation of application No. 17/818,876, filed on Aug. 10, 2022, granted, now 11,630,605.
Prior Publication US 2024/0053919 A1, Feb. 15, 2024
Int. Cl. G06F 3/06 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01); H03K 19/173 (2006.01)
CPC G06F 3/0656 (2013.01) [G06F 3/0611 (2013.01); G06F 3/064 (2013.01); G06F 3/0673 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01); H03K 19/1737 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a memory bank;
a first buffer for storing a read-modify-write request comprising a read address, a write address and a first operand, the first buffer including a write address output, a read address output and a data output;
a second buffer for storing the write address and the first operand, wherein a first input of the second buffer is connected to the write address output of the first buffer, and a second input of the second buffer is connected to the data output of the first buffer;
a combiner circuit for computing intermediary data based on the first operand stored at the second buffer and a second operand read from a first location of the memory bank as specified by the read address;
an activation function circuit for computing activation data based on the intermediary data, wherein the write address specifies a second location in the memory bank where the activation data is written;
a first multiplexor, wherein a first input of the first multiplexor is connected to the data output of the first buffer and a second input of the first multiplexor is connected to an output of the activation function circuit; and
a second multiplexor, wherein a first input of the second multiplexor is connected to a write address output of the second buffer, a second input of the second multiplexor is connected to the write address output of the first buffer, and a third input of the second multiplexor is connected to a read address output of the first buffer.