US 12,271,622 B2
Processor using host memory buffer and storage system including the processor
Jinhwan Choi, Seoul (KR); Byungki Lee, Hwaseong-si (KR); Junhee Kim, Suwon-si (KR); Sunghyun Noh, Seoul (KR); Keunsan Park, Hwaseong-si (KR); Jekyeom Jeon, Siheung-si (KR); and Jooyoung Hwang, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jan. 12, 2022, as Appl. No. 17/647,745.
Claims priority of application No. 10-2021-0004938 (KR), filed on Jan. 13, 2021; and application No. 10-2021-0064637 (KR), filed on May 20, 2021.
Prior Publication US 2022/0222011 A1, Jul. 14, 2022
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0656 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A processor configured to control a storage device, the processor comprising:
at least one host write buffer generated based on device information of the storage device, the device information including at least one of a program method of the storage device and a unit of interleaving processing for simultaneously processing a request received from a host;
meta-memory buffer configured to merge write commands of non-consecutive logical block addresses; and
a control module configured to control the at least one host write buffer,
wherein the control module is further configured to store, in the at least one host write buffer, a plurality of write commands and merge the plurality of write commands to generate a merged write command,
wherein the meta-memory buffer is further configured to be dynamically allocated according to a number of write commands merged in the at least one host write buffer and store meta information including at least one of a logical block address and length information of data corresponding to each of the write commands.