US 12,271,620 B2
Techniques for improved write performance modes
David Aaron Palmer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 28, 2023, as Appl. No. 18/521,693.
Claims priority of provisional application 63/385,491, filed on Nov. 30, 2022.
Prior Publication US 2024/0176534 A1, May 30, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/061 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a controller associated with a memory system comprising a plurality of non-volatile memory cells arranged in a plurality of logical units, the controller configured to cause the apparatus to:
receive, at the memory system while operating in a first performance mode, a command associated with a second performance mode;
abort, at the memory system and based at least in part on the command, one or more memory management operations associated with first data stored in the plurality of non-volatile memory cells;
receive, at the memory system while operating in the second performance mode, a write command and second data associated with the write command; and
write the second data associated with the write command to a logical unit associated with the second performance mode.