US 12,271,618 B2
Identifying center of valley in memory systems
Kyungjin Kim, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 24, 2022, as Appl. No. 17/972,174.
Prior Publication US 2024/0134559 A1, Apr. 25, 2024
Prior Publication US 2024/0231673 A9, Jul. 11, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0653 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a set of memory components; and
a processing device, operatively coupled to the set of memory components, configured to perform operations comprising:
detecting a read error associated with reading data from the set of memory components in accordance with an individual read level of a plurality of read levels; and
in response to detecting the read error:
generating a plurality of bins as a function of a plurality of check failure bit (CFBit) count values corresponding to a set of read levels adjacent to the individual read level;
adjusting the plurality of bins based on one or more error count values computed by reading data from the set of memory components using the plurality of bins;
computing a center of valley (CoV) for the individual read level based on a pair of read levels defined by a set of the plurality of bins; and
updating a read level used to read the data from the set of memory components based on the computed CoV.