US 12,271,616 B2
Independently controlled DMA and CPU access to a shared memory region
Utkarsh Y. Kakaiya, Folsom, CA (US); David Koufaty, Portland, OR (US); Rajesh Sankaran, Portland, OR (US); and Vedvyas Shanbhogue, Austin, TX (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 15, 2021, as Appl. No. 17/348,586.
Prior Publication US 2022/0398017 A1, Dec. 15, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 13/28 (2006.01)
CPC G06F 3/065 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G06F 13/28 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory;
a processor core;
a processor memory management unit (MMU) communicatively coupled to the memory and the processor core; and
an input/output memory management unit (IOMMU) communicatively coupled to the memory and the processor core, the processor MMU and the IOMMU including circuitry to:
share page tables associated with a page between the processor MMU and the IOMMU;
store a page table entry in the memory associated with the page;
separately control access to the page from the processor core and from a direct memory access (DMA) request based on one or more fields of the stored page table entry; and
perform a copy-on-read operation for an input/output device access to the page based on the one or more fields of the stored page table entry.