US 12,271,512 B2
Method and device for authenticating an FPGA configuration
Fabrizio De Santis, Munich (DE); and Markus Dichtl, Neu-Ulm (DE)
Assigned to Siemens Aktiengesellschaft, Munich (DE)
Appl. No. 17/413,090
Filed by Siemens Aktiengesellschaft, Munich (DE)
PCT Filed Nov. 19, 2019, PCT No. PCT/EP2019/081783
§ 371(c)(1), (2) Date Jun. 11, 2021,
PCT Pub. No. WO2020/120079, PCT Pub. Date Jun. 18, 2020.
Claims priority of application No. 18212529 (EP), filed on Dec. 14, 2018; and application No. 19154671 (EP), filed on Jan. 31, 2019.
Prior Publication US 2022/0043900 A1, Feb. 10, 2022
Int. Cl. G06F 21/76 (2013.01); G06F 21/44 (2013.01); G06F 21/57 (2013.01); H04L 9/32 (2006.01)
CPC G06F 21/76 (2013.01) [G06F 21/44 (2013.01); G06F 21/57 (2013.01); H04L 9/3236 (2013.01); H04L 9/3278 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method for authenticating a Field Programmable Gate Array (FPGA) configuration, the method comprising:
at least partially reading the FPGA configuration of an FPGA by the FPGA itself;
calculating a first checksum over the FPGA configuration which has been read;
comparing the first checksum with a predefined checksum stored in a storage unit; and
providing an authentication response which confirms that the FPGA configuration is authentic when the first checksum corresponds to the predefined checksum,
wherein the reading, the calculating, the comparing, and the providing are performed in obfuscated form such that an attacker cannot distinguish between the authentication response or a self-check of the FPGA,
wherein the authentication response which confirms that the FPGA configuration is authentic is provided with a non-zero degree of probability that is less than or equal to 2−32 when the first checksum and the predefined checksum do not correspond,
wherein the first checksum is provided when a specific item of information is transmitted to the FPGA, and
wherein the specific item of information comprises one signal or a multiplicity of signals, wherein the same one signal is applied or each signal of the same multiplicity of signals is applied to all inputs of a multiplicity of inputs of the FPGA configuration.