US 12,271,363 B2
Optimal dynamic shard creation in storage for graph workloads
Seyedeh Hanieh Hashemi, Los Angeles, CA (US); Joo Hwan Lee, San Jose, CA (US); and Yang Seok Ki, Palo Alto, CA (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 12, 2019, as Appl. No. 16/274,232.
Claims priority of provisional application 62/780,186, filed on Dec. 14, 2018.
Prior Publication US 2020/0192880 A1, Jun. 18, 2020
Int. Cl. G06F 16/22 (2019.01); G06F 16/23 (2019.01); G06F 16/2455 (2019.01); G06F 16/28 (2019.01); G06F 16/901 (2019.01)
CPC G06F 16/2272 (2019.01) [G06F 16/23 (2019.01); G06F 16/2456 (2019.01); G06F 16/287 (2019.01); G06F 16/9024 (2019.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a storage drive comprising:
a host processor interface circuit configured to communicate data and commands with an external host processor circuit;
a controller processor circuit configured to:
send shards including graph data elements, from the storage drive, to the host processor circuit using the host processor interface circuit to determine, based on processing at the host processor circuit:
a first active graph data element is active based on a variation of the first active graph data element satisfying an active element threshold and the first active graph data element having a first state and a second state that is different from the first state; and
a second active graph data element is active based on a variation of the second active graph data element satisfying the active element threshold and the second active graph data element having a third state and a fourth state that is different than the third state,
receive, at the storage drive, using the host processor interface circuit, the first active graph data element and the second active graph data element from the host processor circuit,
include, based on processing at the controller processor circuit, the first active graph data element in a first dynamic shard and the second active graph data element in a second dynamic shard, and
merge, based on processing at the controller processor circuit offloaded from the host processor circuit, at least a portion of the first dynamic shard and at least a portion of the second dynamic shard into a merged dynamic shard, wherein the controller processor circuit performs the merge based on a determination that the host processor circuit has entered a process stage; and
a non-volatile memory configured to store data in an at least a partial graph structure, wherein the graph structure includes data elements that include vertexes and an edge, and wherein sub-portions of the data elements are grouped into shards;
wherein the merged dynamic shard comprises the first one of the active graph data elements and the second one of the active graph data elements.