US 12,271,332 B2
Redundancy scheme for activating circuitry on a base die of a 3D stacked device
Brian C. Gaide, Erie, CO (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Mar. 30, 2023, as Appl. No. 18/128,936.
Prior Publication US 2024/0330222 A1, Oct. 3, 2024
Int. Cl. G06F 13/40 (2006.01); H01L 25/065 (2023.01); H10B 80/00 (2023.01)
CPC G06F 13/4027 (2013.01) [H01L 25/0657 (2013.01); H10B 80/00 (2023.02); H01L 2225/06565 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A 3D stacked device, comprising:
a plurality of semiconductor chips stacked vertically on each other, wherein each of the plurality of semiconductor chips is logically divided into a same of number of portions, wherein respective first portions from the plurality of semiconductor chips in a first column are grouped together to form a first sliver and respective second portions from the plurality of semiconductor chips in a second column are grouped together to form a second sliver,
wherein the first sliver and the second sliver are coupled together through inter-chip bridges, wherein at least one of the inter-chip bridges provides at least three communication paths to selectively route data to one of: a portion on a same semiconductor chip, a portion on an upper semiconductor chip, and a portion on a lower semiconductor chip,
wherein each of the respective first portions in the first sliver comprises a first block and a second block coupled to the first block through a respective inter-block bridge, wherein each respective inter-block bridge provides at most two communication paths to selectively route data to one of: a block on a same semiconductor chip and to a block on a different semiconductor chip,
wherein the respective first blocks from the plurality of semiconductor chips in a first sub-column are grouped together to form a first sub-sliver, wherein the first blocks in the first sub-sliver comprise an active first block,
wherein the respective second blocks from the plurality of semiconductor chips in a second sub-column are grouped together to form a second sub-sliver, wherein the second blocks in the second sub-sliver comprise an active second block and a deactivated second block,
wherein a communication path of the respective inter-block bridge is configured to route data from the active first block in the first sub-sliver to the active second block in the second sub-sliver, wherein the active first block is in a same semiconductor chip as the deactivated second block but in a different semiconductor chip from the active second block.