US 12,271,329 B2
Multi-port memory link expander to share data among hosts
Zhuangzhi Li, Shanghai (CN); Jie Bai, Shanghai (CN); Di Zhang, Shanghai (CN); Changcheng Liu, Shanghai (CN); and Zhonghua Sun, Shanghai (CN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 18/250,325
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Nov. 24, 2020, PCT No. PCT/CN2020/131066
§ 371(c)(1), (2) Date Apr. 24, 2023,
PCT Pub. No. WO2022/109770, PCT Pub. Date Jun. 2, 2022.
Prior Publication US 2023/0385220 A1, Nov. 30, 2023
Int. Cl. G06F 13/40 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01)
CPC G06F 13/4022 (2013.01) [G06F 13/1663 (2013.01); G06F 13/4081 (2013.01); G06F 13/4221 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A computing system comprising:
a memory expander including a coherent device memory, a memory controller coupled to the coherent device memory, and a plurality of host paths coupled to the memory controller, wherein the memory controller is to initialize the coherent device memory as hot-pluggable memory;
a plurality of host devices coupled to the memory expander, the plurality of host devices including a first host device having a set of executable program instructions, which when executed by the first host device, cause the first host device to:
collect, by a basic input output system (BIOS), memory information from a first host path of the plurality of host paths to the coherent device memory,
transfer the memory information from the BIOS to an operating system (OS) via one or more OS interface tables, and
initialize, by the OS, the memory expander based on the memory information, wherein the memory information includes memory capabilities and configuration settings associated with the memory expander.
 
8. A memory expander comprising:
a coherent device memory;
a memory controller coupled to the coherent device memory; and
a plurality of host paths coupled to the memory controller, wherein the memory controller is to initialize the coherent device memory as hot-pluggable memory, and wherein the plurality of host paths includes:
a first host path including a first port and a first coherence agent; and
a second host path including a second port and a second coherence agent;
wherein the memory expander is to report address mapping information to a plurality of host devices.
 
12. At least one non-transitory computer readable storage medium comprising a set of executable program instructions which, when executed by a host device, cause the host device to:
collect, by a basic input output system (BIOS), memory information from a first host path to a coherent device memory on a memory expander, wherein the memory expander includes a plurality of host paths;
transfer the memory information from the BIOS to an operating system (OS) via one or more OS interface tables; and
initialize, by the OS, the memory expander based on the memory information, wherein the memory information includes memory capabilities and configuration settings associated with the memory expander.
 
18. A method comprising:
collecting, by a basic input output system (BIOS), memory information from a first host path to a coherent device memory on a memory expander, wherein the memory expander includes a plurality of host paths;
transferring the memory information from the BIOS to an operating system (OS) via one or more OS interface tables; and
initializing, by the OS, the memory expander based on the memory information, wherein the memory information includes memory capabilities and configuration settings associated with the memory expander.