US 12,271,327 B2
Device, system, and method for inspecting direct memory access requests
Kaijie Guo, Shanghai (CN); Xin Zeng, Shanghai (CN); Ned Smith, Beaverton, OR (US); Weigang Li, Shanghai (CN); Junyuan Wang, Shanghai (CN); Songwu Shen, Shanghai (CN); Zijuan Fan, Shanghai (CN); Yao Huo, Shanghai (CN); Maksim Lukoshkov, Clarecastle Clare (IE); and Laurent Coquerel, Limerick (IE)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 18/035,705
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Dec. 24, 2020, PCT No. PCT/CN2020/138920
§ 371(c)(1), (2) Date May 5, 2023,
PCT Pub. No. WO2022/133879, PCT Pub. Date Jun. 30, 2022.
Prior Publication US 2023/0418773 A1, Dec. 28, 2023
Int. Cl. G06F 13/28 (2006.01)
CPC G06F 13/28 (2013.01) 14 Claims
OG exemplary drawing
 
1. A device comprising:
a first hardware interface to couple the device to an input-output memory management unit (IOMMU);
a second hardware interface to couple the device to a first endpoint device;
manager circuitry to create entries of a registry of accessible addresses, the entries each based on a respective one of first messages received via the first hardware interface, wherein the first messages each indicate a completion of a respective address translation, the entries each to indicate an accessibility of a respective address by a respective endpoint device of one or more endpoint devices including the first endpoint device; and
controller circuitry coupled to the manager circuitry, the first hardware interface, and the second hardware interface, the controller circuitry to receive a direct memory access (DMA) request from the first endpoint device, to signal the manager circuitry to perform an address search of the registry based on the DMA request, and to selectively signal, based on the address search, whether an operation with the DMA request is to be performed.