US 12,271,320 B2
Apparatus and method using plurality of physical address spaces
Jason Parker, Sheffield (GB); Andrew Brookfield Swaine, Sheffield (GB); Yuval Elad, Cambridge (GB); and Martin Weidmann, Cambridge (GB)
Assigned to Arm Limited, Cambridge (GB)
Appl. No. 17/906,625
Filed by ARM LIMITED, Cambridge (GB)
PCT Filed Jan. 26, 2021, PCT No. PCT/GB2021/050173
§ 371(c)(1), (2) Date Sep. 19, 2022,
PCT Pub. No. WO2021/191575, PCT Pub. Date Sep. 30, 2021.
Claims priority of application No. 2004258 (GB), filed on Mar. 24, 2020.
Prior Publication US 2023/0176983 A1, Jun. 8, 2023
Int. Cl. G06F 12/14 (2006.01); G06F 12/0808 (2016.01); G06F 12/1045 (2016.01)
CPC G06F 12/1425 (2013.01) [G06F 12/0808 (2013.01); G06F 12/1063 (2013.01); G06F 12/1458 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
address translation circuitry to translate a target virtual address specified by a memory access request issued by requester circuitry into a target physical address; and
requester-side filtering circuitry to perform a granule protection lookup based on the target physical address and a selected physical address space associated with the memory access request, to determine whether to allow the memory access request to be passed to a cache or passed to an interconnect for communicating with a completer device for servicing the memory access request, where said selected physical address space is one of a plurality of physical address spaces; in which:
in the granule protection lookup, the requester-side filtering circuitry is configured to:
obtain granule protection information corresponding to a target granule of physical addresses including the target physical address, the granule protection information indicative of at least one allowed physical address space associated with the target granule; and
block the memory access request when the granule protection information indicates that the selected physical address space is not one of said at least one allowed physical address space;
the apparatus comprising a point of physical aliasing (PoPA) memory system component configured to de-alias a plurality of aliasing physical addresses from different physical address spaces which correspond to the same memory system resource, to map any of the plurality of aliasing physical addresses to a de-aliased physical address to be provided to at least one downstream memory system component; and
at least one pre-PoPA memory system component provided upstream of the PoPA memory system component, where the at least one pre-PoPA memory system component is configured to treat the aliasing physical addresses from different physical address spaces as if the aliasing physical addresses correspond to different memory system resources.