US 12,271,317 B2
Creating high density logical to physical mapping
Stephen Hanna, Fort Collins, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 7, 2024, as Appl. No. 18/598,978.
Application 18/598,978 is a continuation of application No. 17/663,255, filed on May 13, 2022, granted, now 11,940,926.
Prior Publication US 2024/0289279 A1, Aug. 29, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/10 (2016.01); G06F 12/02 (2006.01); G06F 12/1009 (2016.01)
CPC G06F 12/1009 (2013.01) [G06F 12/0246 (2013.01); G06F 2212/7201 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
generate a set of entries, each entry of the set of entries indicating a mapping between a logical address of a set of logical addresses and a physical address of a set of physical addresses, the set of entries associated with a first level of a mapping information; and
store a coalesced entry comprising a subset of logical addresses in a second level of the mapping information based at least in part on generating the set of entries, the coalesced entry indicating the mapping between the set of logical addresses and the set of physical addresses based at least in part on the subset of logical addresses being sequential.