US 12,271,306 B2
Integrated three-dimensional (3D) DRAM cache
Wilfred Gomes, Portland, OR (US); Adrian C. Moga, Portland, OR (US); and Abhishek Sharma, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 27, 2021, as Appl. No. 17/214,835.
Prior Publication US 2022/0308995 A1, Sep. 29, 2022
Int. Cl. G06F 12/00 (2006.01); G06F 12/0802 (2016.01)
CPC G06F 12/0802 (2013.01) [G06F 2212/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first die comprising a three-dimensional (3D) DRAM cache, wherein:
the 3D DRAM cache comprises a first layer and a second layer over the first layer, wherein the second layer is one of multiple layers comprising DRAM cells, wherein the multiple layers comprising the DRAM cells are coupled with one another with vias through the multiple layers,
one of the first layer and the second layer comprises PMOS transistors, and another of the first layer and the second layer comprises NMOS transistors, and
the 3D DRAM cache comprises CMOS control circuitry comprising a first transistor of the first layer and a second transistor of the second layer; and
a second die stacked and bonded with the first die in a package, wherein the second die comprises compute logic comprising one or more processor cores.